The present invention relates to a logic circuit formed in a semiconductor integrated circuit device and, more particularly, to a technique which is effective if applied to a high-speed logic circuit including a bipolar transistor and an insulated gate type field effect transistor (which will be shortly referred to as the "MOSFET").
An emitter coupled logic (which will be shortly referred to as the "ECL") circuit can operate at a high speed because its output signal can have its amplitude reduced. However, this ECL circuit has a high power consumption because it includes a constant current supply transistor rendered conductive at all times.
On the other hand, a CMOS (or complementary MOS) circuit formed of P-channel and N-channel MOSFETs has a low power consumption because only one of the P-channel and N-channel MOSFETs is rendered conductive in response to an input signal. Since, however, the amplitude of the output signal of the CMOS circuit is substantially equal to the voltage difference between a power supply voltage (V.sub.DD) and a ground potential (V.sub.SS) coupled to the CMOS circuit, the time period required for charging and discharging a load capacitance coupled to the output of the CMOS circuit is long. As a result, the operating speed of the CMOS circuit is dropped to a low value. In the case of the CMOS circuit, moreover, the CMOS circuit has its propagation delay time elongated to the higher value for the higher level of the load capacitance coupled to the output of the CMOS circuit.
As a logic circuit having both the high speed of the aforementioned ECL circuit and the low power consumption of the CMOS circuit, there has been highlighted in recent years a bipolar CMOS logic circuit (which may be shortly referred to as the "BiCMOS circuit") which is formed by coupling a bipolar transistor and the CMOS circuit. This BiCMOS circuit is disclosed in the Japanese Patent Laid-Open No. 59 - 11034 (which corresponds to the U.S. Pat. No. 4,719,373), for example. This BiCMOS circuit is constructed of: a pair of output bipolar transistors coupled in the form of a totem pole between the power supply voltage (V.sub.DD) and the ground voltage (V.sub.SS); and a CMOS circuit coupled to the respective bases of the output bipolar transistors to effect the push-pull operations of the same. For these operations, the output signal of the BiCMOS circuit is set at a high level such as (V.sub.DD - V.sub.BE) and at a low level such as (V.sub.SS - V.sub.BE). Here, the V.sub.BE designates the base-emitter potential of the bipolar transistor. Therefore, the high and low levels of the output signal are determined at 4.3 V and 0.7 V, respectively, in case the power supply voltage (V.sub.DD), the ground voltage (V.sub.SS) and the base-emitter voltage (V.sub.SS) are set at 5 V, 0 V and 0.7 V, respectively.
The logic circuit formed by combining the bipolar transistor and the MOSFET is exemplified by: the circuit which is shown in FIG. 7 of the U.S. Pat. No. 3,609,479 issued on Sept. 24, 1971; or the circuit which is disclosed in the Japanese Patent Application No. 61 - 308456 filed on Dec. 26, 1986 by Hitachi, Ltd., (which corresponds to the U.S. patent application No. 132,368 filed on Dec. 14, 1987 and Korean Patent Application No. 1987 - 14711).
On the other hand, the NAND circuit formed of the bipolar transistor is disclosed in FIG. 1 of the Japanese Patent Laid-Open No. 54 - 87160 laid open on July 11, 1979. The NAND circuit formed of the MOSFET is disclosed in FIG. 2(a) of "A High-Speed Ultra-Low Power 64K CMOS EPROM with On-Chip Test Functions" reported by Mark W. Knecht et al on pp. 554 to 561 of IEEE JOURNAL OF SOLID-STATE CIRCUIT, Vol. SC-18, No. 5, October 1983.